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advanced communications & sensing rev 8 C 18 th feb. 2009 www.semtech.com 1 sx1501/SX1502/sx1503 4/8/16 channel low voltage gpio sx1501/SX1502/sx1503 4/8/16 channel low voltage gpio with nint and nrese t g eneral d escription the sx1501, SX1502 and sx1503 are complete ultra low voltage general purpose parallel input/output (gpio) expanders ideal for low power handheld battery powered equipment. they allow easy serial expansion of i/o through a standard i 2 c interface. gpio devices can provide additional control and monitoring when the microcontroller or chipset has insufficient i/o ports, or in systems where serial communication and control from a remote location is advantageous. these devices can also act as a level shifter to connect a microcontroller running at one voltage le vel to a component running at a different voltage level . the core is operating as low as 1.2v while the i/o banks can operate between 1.2v and 5.5v independent of the core voltage and each other. each gpio is programmable via 8-bit configuration registers. data registers, direction registers, pul l- up/pull-down registers, interrupt mask registers an d interrupt registers allow the system master to program and configure 4 or 8 or 16-gpios using a standard 400khz i 2 c interface. the sx1501, SX1502 and sx1503 offer a unique fully programmable logic functions like a pld to gi ve more flexibility and reduce external logic gates us ed for standard applications. the sx1501, SX1502 and sx1503 have the ability to generate mask-programmable interrupts based on falling/rising edge of any of its gpio lines. a dedicated pin indicates to a host controller that a state change occurred in one or more of the gpio lines. the sx1501, SX1502 and sx1503 each come in a small qfn-ut-20/28 package as well as a tssop- 20/28 package. all devices are rated from -40c to +85c temperature range. o rdering i nformation part number i/o channels package sx1501i087trt 4 qfn-ut-20 SX1502i087trt 8 qfn-ut-20 sx1503i091trt 16 qfn-ut-28 sx1501i088trt (1) 4 tssop-20 SX1502i088trt (1) 8 tssop-20 sx1503i089trt (1) 16 tssop-28 SX1502evk (2) 8 evaluation kit (1) future products (2) SX1502i087trt based, unique evaluation kit for the three parts. k ey p roduct f eatures 4/8/16 channel of i/os true bi-directional style i/o programmable pull-up/pull-down push/pull outputs 1.2v to 5.5v independent operating voltage for all supply rails (vddm, vcc1, vcc2) 5.5v compatible i/os, up to 24ma output sink (no total sink current limit) fully programmable logic functions (pld) 400khz 2-wire i 2 c compatible slave interface open drain active low interrupt output (nint) bit maskable programmable edge sensitivity power-on reset and reset input (nreset) ultra low current consumption of typ. 1ua -40c to +85c operating temperature range ultra-thin 3x3mm qfn-ut-20 and tssop-20 packages (sx1501/SX1502) ultra-thin 4x4mm qfn-ut-28 and tssop-28 packages (sx1503) t ypical a pplications cell phones, pdas, mp3 players digital camera portable multimedia player notebooks gps units industrial, ate any battery powered equipment
advanced communications & sensing rev 8 C 18 th feb. 2009 www.semtech.com 2 sx1501/SX1502/sx1503 4/8/16 channel low voltage gpio table of contents g eneral d escription ................................................... ................................................... ............... 1 o rdering i nformation ................................................... ................................................... ............. 1 k ey p roduct f eatures ................................................... ................................................... ............ 1 t ypical a pplications ................................................... ................................................... ............... 1 1 p in description ................................................... ................................................... ................ 4 1.1 sx1501 4-channel gpio 4 1.2 SX1502 8-channel gpio 5 1.3 sx1503 16-channel gpio 6 2 e lectrical c haracteristics ................................................... ............................................ 7 2.1 absolute maximum ratings 7 2.2 electrical specifications 7 2.2.1 increasing i/o sink and source current capabilities (boost mode) 9 3 t ypical o perating c haracteristics ................................................... ............................ 10 3.1 iddm vs. vddm 10 3.2 vol vs. iol 10 3.3 voh vs. ioh 11 3.4 icc1+icc2 vs. vcc1,2 when boost mode is on 12 4 b lock d etailed d escription ................................................... .......................................... 13 4.1 sx1501 4-channel gpio 13 4.2 SX1502 8-channel gpio 13 4.3 sx1503 16-channel gpio 14 4.4 reset (nreset) 14 4.5 2-wire interface (i 2 c) 15 4.5.1 write 15 4.5.2 read 16 4.5.3 read - stop separated format (sx1501 and SX1502 onl y) 16 4.6 interrupt (nint) 17 4.7 programmable logic functions (pld) 17 4.7.1 sx1501 17 4.7.2 SX1502 18 4.7.3 sx1503 18 4.7.4 tutorial 18 5 c onfiguration r egisters ................................................... ............................................... 20 5.1 sx1501 4-channel gpio 20 5.2 SX1502 8-channel gpio 21 5.3 sx1503 16-channel gpio 23 6 a pplication i nformation ................................................... ................................................ 27 6.1 typical application circuit 27 6.2 typical led operation 27 6.2.1 led on/off control 27 6.2.2 led intensity control 28 6.3 keypad implementation 28 6.4 level shifter implementation hints 28
advanced communications & sensing rev 8 C 18 th feb. 2009 www.semtech.com 3 sx1501/SX1502/sx1503 4/8/16 channel low voltage gpio 7 p ackaging i nformation ................................................... .................................................. 2 9 7.1 qfn-ut 20-pin outline drawing 29 7.2 qfn-ut 20-pin land pattern 29 7.3 qfn-ut 28-pin outline drawing 30 7.4 qfn-ut 28-pin land pattern 30 7.5 tssop 20-pin outline drawing 30 7.6 tssop 20-pin land pattern 31 7.7 tssop 28-pin outline drawing 32 7.8 tssop 28-pin land pattern 32 8 s oldering p rofile ................................................... ................................................... ........ 33
advanced communications & sensing rev 8 C 18 th feb. 2009 www.semtech.com 4 sx1501/SX1502/sx1503 4/8/16 channel low voltage gpio 1 p in description 1.1 sx1501 4-channel gpio pin symbol type description 1 nreset dio active low reset 2 sda dio i 2 c serial data line 3 nc1 - leave open, not connected 4 scl di i 2 c serial clock line 5 i/o[0] dio (*1) i/o[0], at power-on configured as an input 6 i/o[1] dio (*1) i/o[1], at power-on configured as an input 7 vcc1 p i/o supply voltage 8 gnd p ground pin 9 i/o[2] dio (*1) i/o[2], at power-on configured as an input high sink i/o. 10 i/o[3] dio (*1) i/o[3], at power-on configured as an input high sink i/o. 11 nint do active low interrupt output 12 addr di address input, connect to vddm or gnd 13 nc2 - leave open, not connected 14 vddm p main supply voltage 15 nc3 - leave open, not connected 16 nc4 - leave open, not connected 17 nc7 - connect to vcc1 18 gnd p ground pin 19 nc5 - leave open, not connected 20 nc6 - leave open, not connected a: analog d: digital i: input o: output p: power (*1) this pin is programmable through the i 2 c interface table 1 C sx1501 pin description figure 1 C sx1501 qfn-ut-20 pinout nreset sda nc1 scl i/o[0] i/o[1] vcc1 gnd i/o[2] i/o[3] nc3 vddm nc2 addr nint nc6 nc5 gnd nc7 nc4 gnd (pad)
advanced communications & sensing rev 8 C 18 th feb. 2009 www.semtech.com 5 sx1501/SX1502/sx1503 4/8/16 channel low voltage gpio 1.2 SX1502 8-channel gpio pin symbol type description 1 nreset dio active low reset 2 sda dio i 2 c serial data line 3 nc1 - leave open, not connected 4 scl di i 2 c serial clock line 5 i/o[0] dio (*1) i/o[0], at power-on configured as an input 6 i/o[1] dio (*1) i/o[1], at power-on configured as an input 7 vcc1 p supply voltage for bank a i/o[0-3] 8 gnd p ground pin 9 i/o[2] dio (*1) i/o[2], at power-on configured as an input high sink i/o. 10 i/o[3] dio (*1) i/o[3], at power-on configured as an input high sink i/o. 11 nint do active low interrupt output 12 addr di address input, connect to vddm or gnd 13 nc2 - leave open, not connected 14 vddm p main supply voltage 15 i/o[4] dio (*1) i/o[4], at power-on configured as an input 16 i/o[5] dio (*1) i/o[5], at power-on configured as an input 17 vcc2 p supply voltage for bank b i/o[4-7] 18 gnd p ground pin 19 i/o[6] dio (*1) i/o[6], at power-on configured as an input 20 i/o[7] dio (*1) i/o[7], at power-on configured as an input a: analog d: digital i: input o: output p: power (*1) this pin is programmable through the i 2 c interface table 2 C SX1502 pin description figure 2 C SX1502 qfn-ut-20 pinout nreset sda nc1 scl i/o[0] i/o[1] vcc1 gnd i/o[2] i/o[3] i/o[4] vddm nc2 addr nint i/o[7] i/o[6] gnd vcc2 i/o[5] gnd (pad)
advanced communications & sensing rev 8 C 18 th feb. 2009 www.semtech.com 6 sx1501/SX1502/sx1503 4/8/16 channel low voltage gpio 1.3 sx1503 16-channel gpio pin symbol type description 1 gnd p ground pin 2 i/o[2] dio (*1) i/o[2], at power-on configured as an input 3 i/o[3] dio (*1) i/o[3], at power-on configured as an input 4 vcc1 p i/o supply voltage for bank a i/o[0-7] 5 i/o[4] dio (*1) i/o[4], at power-on configured as an input 6 i/o[5] dio (*1) i/o[5], at power-on configured as an input 7 gnd p ground pin 8 i/o[6] dio (*1) i/o[6], at power-on configured as an input high sink i/o. 9 i/o[7] dio (*1) i/o[7], at power-on configured as an input high sink i/o. 10 nint do active low interrupt output 11 nc - leave open, not connected 12 vddm p main supply voltage 13 i/o[8] dio (*1) i/o[8], at power-on configured as an input 14 i/o[9] dio (*1) i/o[9], at power-on configured as an input 15 gnd p ground pin 16 i/o[10] dio (*1) i/o[10], at power-on configured as an input 17 i/o[11] dio (*1) i/o[11], at power-on configured as an input 18 vcc2 p i/o supply voltage for bank b i/o[8-15] 19 i/o[12] dio (*1) i/o[12], at power-on configured as an input 20 i/o[13] dio (*1) i/o[13], at power-on configured as an input 21 gnd p ground pin 22 i/o[14] dio (*1) i/o[14], at power-on configured as an input high sink i/o. 23 i/o[15] dio (*1) i/o[15], at power-on configured as an input high sink i/o. 24 nreset dio active low reset 25 sda dio i 2 c serial data line 26 scl di i 2 c serial clock line 27 i/o[0] dio (*1) i/o[0], at power-on configured as an input 28 i/o[1] dio (*1) i/o[1], at power-on configured as an input a: analog d: digital i: input o: output p: power (*1) this pin is programmable through the i 2 c interface table 3 C sx1503 pin description figure 3 C sx1503 qfn-ut-28 pinout 21 20 19 18 17 16 15 28 27 26 25 24 23 22 8 9 10 11 12 13 14 gnd i/o[2] i/o[3] vcc1 i/o[4] i/o[5] gnd i/o[6] i/o[7] nint nc vddm i/o[8] i/o[9] gnd i/o[13] i/o[12] vcc2 i/o[11] i/o[10] gnd i/o[1] i/o[0] scl sda nreset i/o[15] i/o[14] top view gnd (pad) 1 2 3 4 5 6 7
advanced communications & sensing rev 8 C 18 th feb. 2009 www.semtech.com 7 sx1501/SX1502/sx1503 4/8/16 channel low voltage gpio 2 e lectrical c haracteristics 2.1 absolute maximum ratings stress above the limits listed in the following tab le may cause permanent failure. exposure to absolut e ratings for extended time periods may affect device reliability . the limiting values are in accordance with the ab solute maximum rating system (iec 134). all voltages are r eferenced to ground (gnd). symbol description min max unit vddm max main supply voltage - 0.4 6.0 v vcc1,2 max i/o banks supply voltage - 0.4 6.0 v v esd_hbm electrostatic handling hbm model (1) - 1500 v v esd_cdm electrostatic handling cdm model - 300 v v esd_mm electrostatic handling mm model - 200 v t a operating ambient temperature range -40 +85 c t c junction temperature range -40 +125 c t stg storage temperature range -55 +150 c i lat latchup-free input pin current (2) +/-100 - ma (1) tested according to jesd22-a114a (2) static latch-up values are valid at maximum tem perature according to jedec 78 specification table 4 - absolute maximum ratings 2.2 electrical specifications table below applies to default registers values (bo ost mode off), unless otherwise specified. typical values are given for t a = +25c, vddm=vcc1=vcc2=3.3v. symbol description conditions min typ max unit supply vddm main supply voltage - 1.2 - 5.5 v vcc1,2 i/o banks supply voltage - 1.2 - 5.5 v iddm main supply current (i 2 c inactive) - - 1 5 a vcc1,2 >= 2v - 1 2 icc1,2 i/o banks supply current (1) vcc1,2 < 2v - 0.5 1 a i/os set as input vih high level input voltage - 0.7* vcc1,2 - vcc1,2 +0.3 v vil low level input voltage - -0.4 - 0.3* vcc1,2 v vhys hysteresis of schmitt trigger - - 0.1* vcc1,2 - v ileak input leakage current assuming no active pull-up/down -1.5 - 1.5 a ci input capacitance - - - 10 pf i/os set as output voh high level output voltage - vcc1,2 C 0.3 - vcc1,2 v vol low level output voltage - -0.4 - 0.3 v vcc1,2 >= 2v - - 8 ioh high level output source current vcc1,2 < 2v - - 0.3 (2) ma vcc1,2 >= 2v - - 24 low level output sink current for the high sink i/os vcc1,2 < 2v - - 6 (2) ma vcc1,2 >= 2v - - 12 iol low level output sink current for the other i/os. vcc1,2 < 2v - - 6 ma t pv output data valid timing cf. figure 9 - - 1.5 s nint (output) vol low level output voltage - - - 0.3 v vddm >= 2v - - 12 iol m low level output sink current vddm < 2v - - 6 ma t iv interrupt valid timing from input data change - - 1 s
advanced communications & sensing rev 8 C 18 th feb. 2009 www.semtech.com 8 sx1501/SX1502/sx1503 4/8/16 channel low voltage gpio symbol description conditions min typ max unit t ir interrupt reset timing from reginterruptsource clearing - - 2 s nreset (input/output) vol low level output voltage - - - 0.3 v vddm >= 2v - - 12 iol m low level output sink current vddm < 2v - - 6 ma vih mr high level input voltage - 0.7* vddm - 5.5 v vil m low level input voltage - -0.4 - 0.3* vddm v vhys m hysteresis of schmitt trigger - - 0.1* vddm - v ileak input leakage current - -1.5 - 1.5 a ci input capacitance - - - 10 pf vpor power-on-reset voltage cf. figure 7 0.7 - 0.9 v vdroph high brown-out voltage cf. figure 7 - vddm-1 - v vdropl low brown-out voltage cf. figure 7 - 0.2 - v t reset reset time cf. figure 7 0.6 - 7 ms t pulse reset pulse from host uc cf. figure 7 300 - - ns addr (input) vih ma high level input voltage - 0.7* vddm - vddm +0.3 v vil m low level input voltage - -0.4 - 0.3* vddm v vhys m hysteresis of schmitt trigger - - 0.1* vddm - v ileak input leakage current - -1.5 - 1.5 a ci input capacitance - - - 10 pf scl (input) and sda (input/output) (3) interface complies with slave f/s mode i 2 c interface as described by philips i 2 c specification version 2.1 dated january, 2000. please refer to that document for more detailed i 2 c specifications. vol low level output voltage - - - 0.3 v vddm >= 2v - - 12 iol m low level output sink current vddm < 2v - - 6 ma vih mr high level input voltage - 0.7* vddm - 5.5 v vil m low level input voltage - -0.4 - 0.3* vddm v f scl scl clock frequency - 0 - 400 khz t hd;sta hold time (repeated) start condition - 0.6 - - s t low low period of the scl clock - 1.3 - - s vddm >= 1.3v 0.6 - - t high high period of the scl clock vddm < 1.3v 1 - - s t su;sta set-up time for a repeated start condition - 0.6 - - s t hd;dat data hold time - 0 (4) - 0.9 (5) s t su;dat data set-up time - 100 (6) - - t r rise time of both sda and scl signals - 20+0.1c b (7) - 300 ns
advanced communications & sensing rev 8 C 18 th feb. 2009 www.semtech.com 9 sx1501/SX1502/sx1503 4/8/16 channel low voltage gpio symbol description conditions min typ max unit t f fall time of both sda and scl signals - 20+0.1c b (7) - 300 ns t su;sto set-up time for stop condition - 0.6 - - s t buf bus free time between a stop and start condition - 1.3 - - s c b capacitive load for each bus line - - - 400 pf v nl noise margin at the low level for each connected device (including hysteresis) - 0.1*vddm - - v v nh noise margin at the high level for each connected device (including hysteresis) - 0.2*vddm - - v miscellaneous rpull programmable pull-up/down resistors for io[0-7] - - 60 - k vcc1,2 & vddm = 5v - - 25 t pld pld propagation delay vcc1,2 & vddm = 1.2v - - 500 ns (1) assuming no load connected to outputs and input s fixed to vcc1,2 or gnd. (2) can be increased in regadvanced register. please refer to 2.2.1 for more details. (3) all values referred to vih mr min and vil m max levels. (4) a device must internally provide a hold time of at least 300ns for the sda signal (referred to vih mr min ) to bridge the undefined region of the falling edge of scl. (5) the maximum t hd;dat has only to be met if the device does not stretch t he low period (t low ) of the scl signal. (6) a fast-mode i 2 c-bus device can be used in a standard-mode i 2 c-bus system, but the requirement t su;dat 3 250 ns must then be met. this will automatically be the case if the device d oes not stretch the low period of the scl signal. if such a device does stretch the low period of the scl signal, it must output the next data bit to th e sda line t r max + t su;dat = 1000 + 250 = 1250 ns (according to the standard-mode i2c-bus s pecification) before the scl line is released. (7) c b = total capacitance of one bus line in pf. if mixe d with hs-mode devices, faster fall-times are allow ed. table 5 C electrical specifications 2.2.1 increasing i/o sink and source current capabilitie s (boost mode) when bit 1 of regadvanced register is set, max ioh and iol spec when vcc1,2 is below vboost can be increased together with iddm and icc1,2 figures as described below. symbol description conditions min typ max unit supply vboost low voltage boost threshold - 2.0 2.2 2.4 v vddm = 5.5v (vcc1,2 < vboost) - 150 250 a iddm main supply current (i 2 c inactive) vddm = 1.2v (vcc1,2 < vboost) - 25 50 ua vcc1 = vboost - 250 350 sx1501/2 vcc1 = 1.2v - 100 200 vcc1 = vboost - 250 400 icc1 i/o bank a supply current sx1503 vcc1 = 1.2v - 100 200 a vcc2 = vboost - 150 250 SX1502 vcc2 = 1.2v - 50 150 vcc2 = vboost - 250 450 icc2 i/o bank b supply current sx1503 vcc2 = 1.2v - 100 200 a i/os set as output vcc1,2 >= vboost - - 8 ioh high level output source current for all i/os vcc1,2 < vboost - - 4 ma vcc1,2 >= vboost - - 24 low level output sink current for the high sink i/os vcc1,2 < vboost - - 12 ma vcc1,2 >= vboost - - 12 iol low level output sink current for the other i/os vcc1,2 < vboost - - 6 ma nint, nreset vddm >= vboost - - 12 iol m low level output sink current for nint, nreset vddm < vboost - - 6 ma table 6 C electrical specifications in boost mode important: regadvanced register doesnt affect any spec when vcc1 and vcc2 are above vboost.
advanced communications & sensing rev 8 C 18 th feb. 2009 www.semtech.com 10 sx1501/SX1502/sx1503 4/8/16 channel low voltage gpio 3 t ypical o perating c haracteristics figures below apply to default registers values (bo ost mode off), tamb, unless otherwise specified. 3.1 iddm vs. vddm iddm vs vddm 0 0. 5 1 1.5 2 2.5 3 3.5 0 1 2 3 4 5 6 vddm (v) iddm (u a) 90c - 40 c 3.2 vol vs. iol vol vs iol (vcc1,2=1.2v, all ios) 0 0.05 0.1 0.15 0 3 4.5 6 7.5 9 iol (ma) vol (v ) tamb * * doesnt vary significantly with temperature 1.5
advanced communications & sensing rev 8 C 18 th feb. 2009 www.semtech.com 11 sx1501/SX1502/sx1503 4/8/16 channel low voltage gpio vol vs iol (vcc1,2=5.5v, high sink ios) 0 0.05 0.1 0.15 0 10 15 20 25 30 iol (ma) vol (v ) tamb * * doesnt vary significantly with temperature 5 3.3 voh vs. ioh voh vs ioh (vcc1,2=1.2v) 1.1 1.18 1.2 0 0.4 0.6 0.8 1 ioh (ma) voh (v ) tamb * * doesnt vary significantly with temperature 0.2 1.16 1.14 1.12 voh vs ioh (vcc1,2=5.5v) 5 5.4 5.5 0 10 20 ioh (ma) voh (v ) tamb * * doesnt vary significantly with temperature 5.1 5.3 5.2
advanced communications & sensing rev 8 C 18 th feb. 2009 www.semtech.com 12 sx1501/SX1502/sx1503 4/8/16 channel low voltage gpio 3.4 icc1+icc2 vs. vcc1,2 when boost mode is on icc1+icc2 vs vcc1,2 (vddm = 1.2v) 0 100 200 300 400 500 600 700 0 0.4 0.8 1.2 1.6 2 2.4 2.8 3.2 3.6 4 4.4 4.8 5.2 tamb - 40 c 90 c icc ( ua ) boost mode on vcc1,2 ( v ) icc1+icc2 vs vcc1,2 (vddm = 5.5v) 0 100 200 300 400 500 0 0.4 0.8 1.2 1.6 2 2.4 2.8 3.2 3.6 4 4.4 4.8 5.2 tamb - 40 c 90 c icc ( ua ) boost mode on vcc1,2 ( v )
advanced communications & sensing rev 8 C 18 th feb. 2009 www.semtech.com 13 sx1501/SX1502/sx1503 4/8/16 channel low voltage gpio 4 b lock d etailed d escription 4.1 sx1501 4-channel gpio input filter reset vddm i 2 c bus control nreset scl sda interrupt 4-bit vcc1 i/o[0] i/o[1] i/o[2] i/o[3] r/w gnd i/o bank a a sx1501 nint addr figure 4 C 4-channel low voltage gpio 4.2 SX1502 8-channel gpio input filter reset vddm i 2 c bus control vcc1 nreset scl sda interrupt 8-bit i/o[0] i/o[1] i/o[2] i/o[3] r/w i/o[4] i/o[5] i/o[6] i/o[7] addr gnd vcc2 i/o bank a a i/o bank b a SX1502 nint figure 5 C 8-channel low voltage gpio
advanced communications & sensing rev 8 C 18 th feb. 2009 www.semtech.com 14 sx1501/SX1502/sx1503 4/8/16 channel low voltage gpio 4.3 sx1503 16-channel gpio i 2 c bus control vcc1 input filter reset vddm nreset scl sda interrupt 8-bit r/w i/o[0] i/o[1] i/o[2] i/o[3] i/o[4] i/o[5] i/o[6] i/o[7] gnd vcc2 i/o bank a a i/o bank b a sx1503 i/o[8] i/o[9] i/o[10] i/o[11] i/o[12] i/o[13] i/o[14] i/o[15] 8-bit r/w nint figure 6 C 16-channel low voltage gpio 4.4 reset (nreset) the sx1501, SX1502 and sx1503 generate their own po wer on reset signal after a power supply is connect ed to the vddm pin. the reset signal is made available for the user at the pin nreset. the rising edge of the nreset indicates that the startup sequence of the s x1501, SX1502 or sx1503 has finished. nreset must b e connected to vddm (or greater) either directly, or via a resistor. undefined t reset nreset vddm vpor t pulse vdroph undefined t reset undefined 1 2 3 4 5 6 2 1 vdropl figure 7 C power-on / brown-out reset conditions 1. device behavior is undefined until vddm rises ab ove vpor, at which point nreset is driven to gnd by the sx1501, SX1502 or sx1503. 2. after t reset , nreset is released (high-impedance) by the sx1501 , SX1502 or sx1503 to allow it to be pulled high by an external resistor. 3. in operation, the sx1501, SX1502 and sx1503 may be reset at anytime by an external device driving nreset low during t pulse . chip can be accessed normally again after nreset rising edge.
advanced communications & sensing rev 8 C 18 th feb. 2009 www.semtech.com 15 sx1501/SX1502/sx1503 4/8/16 channel low voltage gpio 4. during a brown-out event, if vddm drops above vd roph a reset will not occur. 5. during a brown-out event, if vddm drops between vdroph and vdropl a reset may occur. 6. during a brown-out event, if vddm drops below vd ropl a reset will occur next time vpor is crossed. please note that a brown-out event is defined as a transient event on vddm. if vddm is attached to a b attery, then the gradual decay of the battery voltage will not be interpreted as a brown-out event. please also note that a sharp rise in vddm (> 1v/us ) may induce a circuit reset. 4.5 2-wire interface (i 2 c) the sx1501, SX1502 and sx1503 2-wire interface (i 2 c compliant) operates only in slave mode. in this configuration, the device has one or two device add resses defined by addr pin. device addr pin i 2 c address description 0 0x2 0 (010000 0 ) first address of the 2-wire interface sx1501 & SX1502 1 0x2 1 (010000 1 ) second address of the 2-wire interface sx1503 0x20 (0100000) fixed address of the 2-wire interfac e table 7 - 2-wire interface address 2 lines are used to exchange data between an extern al master host and the slave device: scl : s erial cl ock sda : s erial da ta the sx1501, SX1502 and sx1503 are read-write slave- mode i 2 c devices and comply with the philips i 2 c standard version 2.1 dated january, 2000. the sx150 1, SX1502 and sx1503 have respectively 12, 16, and 31 user-accessible internal 8-bit registers. the i 2 c interface has been designed for program flexibili ty, in that once the slave address has been sent to the sx1501, sx15 02 or sx1503 enabling it to be a slave transmitter/receiver, any register can be written o r read independently of each other. while there is no auto increment/decrement capability in the sx1501 and sx 1502 i 2 c logic, a tight software loop can be designed to access the next register independent of which regis ter you begin accessing. sx1503 implements auto inc rement capability. the start and stop commands frame the d ata-packet and the repeat start condition is allowe d if necessary. seven bit addressing is used and ten bit addressing is not allowed. any general call address will be i gnored by the sx1501, SX1502 and sx1503. the sx1501, SX1502 a nd sx1503 are not cbus compatible and can operate in standard mode (100kbit/s) or fast mode ( 400kbit/s). 4.5.1 write the simplest format for an i 2 c write is given below. after the start condition [ s], the slave address is sent, followed by an eighth bit indicating a write. the i 2 c then acknowledges that it is being addressed, and the master responds with an 8 bit data byte consisting of the register address. the slave acknowledges and the ma ster sends the appropriate 8 bit data byte. once again t he slave acknowledges and the master terminates the transfer with the stop condition [p]. master operations sx1501, SX1502 or sx1503 operations (slave) s: start condition slave address: 7 bit w: write = 0 register address: 8 bit a: acknowledge (sent by slave) data: 8 bit p: stop condition figure 8 - 2-wire serial interface, write register operation
advanced communications & sensing rev 8 C 18 th feb. 2009 www.semtech.com 16 sx1501/SX1502/sx1503 4/8/16 channel low voltage gpio figure 9 C write regdata register please note that sx1503 implements register address auto-increment i.e. after the data ack from slave the master can write further bytes and the interface wi ll handle the register address increment automatica lly. finally the master terminates the transfer normally the sto p condition [p]. 4.5.2 read after the start condition [s], the slave address is sent, followed by an eighth bit indicating a write . the i 2 c then acknowledges that it is being addressed, and the ma ster responds with an 8 bit data byte consisting of the register address. the slave acknowledges and the ma ster sends the repeated start condition [sr]. once again, the slave address is sent, followed by an eighth bi t indicating a read. the slave responds with an ack nowledge and the previously addressed 8 bit data byte; the m aster then sends a non-acknowledge (nack). finally, the master terminates the transfer with the stop condit ion [p]. master operations sx1501, SX1502 or sx1503 operations (slave) s: start condition slave address: 7 bit w: write = 0 register address: 8 bit r: read = 1 data: 8 bit a: acknowledge (sent by slave) nack: non-acknowledge (sent by master) sr: repeated start condition p: stop condition figure 10 - 2-wire serial interface, read register operation please note that sx1503 implements register address auto-increment i.e. after the data byte from slave the master can acknowledge (ack) to indicate that it wa nts to read the next byte and the interface will ha ndle the register address increment automatically. finally t he master terminates the transfer normally with a n ack followed by the stop condition [p]. 4.5.3 read - stop separated format (sx1501 and SX1502 on ly) when operating sx1501 or SX1502, stop-separated rea ds can also be used. this format allows a master to set up the register address pointer for a read and retu rn to that slave at a later time to read the data. in this format the slave address followed by a write command are s ent after a start [s] condition. the slave then ack nowledges it is being addressed, and the master responds with the 8-bit register address. the master sends a sto p or restart condition and may then address another slav e. after performing other tasks, the master can sen d a start or restart condition to the slave with a read comma nd. the slave acknowledges this request and returns the data from the register location that had previously been set up.
advanced communications & sensing rev 8 C 18 th feb. 2009 www.semtech.com 17 sx1501/SX1502/sx1503 4/8/16 channel low voltage gpio master operations sx1501, SX1502 or sx1503 operations (slave) s: start condition slave address: 7 bit w: write = 0 register address: 8 bit r: read = 1 data: 8 bit a: acknowledge (sent by slave) nack: non-acknowledge (sent by master) sr: repeated start condition p: stop condition figure 11 - 2-wire serial interface, read C stop se parated mode operation 4.6 interrupt (nint) at start-up, the transition detection logic is rese t, and nint is released to a high-impedance state. the interrupt mask register is set to 0xff, disabling the interru pt output for transitions on all i/o ports. the tra nsition flags are cleared to indicate no data changes. an interrupt nint can be generated on any programme d combination of i/os rising and/or falling edges t hrough the reginterruptmask and regsense registers. if needed, the i/os which triggered the interrupt c an then be identified by reading reginterruptsource register. when nint is low (i.e. interrupt occurred), it can be reset back high (i.e. cleared) by writing 0xff i n reginterruptsource (this will also clear correspond ing bits in regeventstatus register). sx1503 also allows the interrupt to be cleared auto matically when reading regdata register (cf. regadv anced) example: we want to detect rising edge of i/o[1] on SX1502 (nint will go low). 1. we enable interrupt on i/o[1] in reginterruptmas k reginterruptmask =xxxxxx 0 x 2. we set edge sense for i/o[1] in regsense regsenselow =xxxx 01 xx 4.7 programmable logic functions (pld) the sx1501, SX1502 and sx1503 offer a unique fully programmable logic functions like a pld to give mor e flexibility and reduce external logic gates used fo r standard applications. since the whole truth table is fully programmable, the sx1501, SX1502, and sx1503 can implement combinatory functions ranging from the basic and/or gates to the most complicated ones with up to four 3-to1 plds or two 3-to-2 plds which can also be externall y cascaded if needed. in all cases, any io not configured for pld functio nality retains its gpio functionality while i/os us ed by the pld have their direction automatically set accordingly. please note that while regdir corresponding bits ar e ignored for pld operation they may still be set t o input to access unused pld inputs as normal gpi (pld truth t able can define some inputs to have no effect on pl d output) and/or generate interrupt based on any of the pld inputs or outputs bits. 4.7.1 sx1501 the sx1501 i/os can be configured to provide any co mbinational 2-to-1 logic function using i/o[0-2] wh ilst retaining gpio capability on i/o[3] or provide a co mbinational 3-to-1 decode function using all 4 i/o ports. regpldmode sx1501 i/os 1:0 3 2 1 0 00 gpio gpio gpio gpio 01 gpio pld out pld in pld in 10 pld out pld in pld in pld in table 8 C sx1501 pld modes settings
advanced communications & sensing rev 8 C 18 th feb. 2009 www.semtech.com 18 sx1501/SX1502/sx1503 4/8/16 channel low voltage gpio 4.7.2 SX1502 the SX1502 i/os can be configured as per the sx1501 , and can additionally be configured to provide a 2-to-1 logic function on i/o[4-6], 3-to-1 logic function o n i/o[4-7], or 3-to-2 logic decode on i/o[0-4]. regpldmode SX1502 i/os 5:4 1:0 7 6 5 4 3 2 1 0 00 00 gpio gpio gpio gpio gpio gpio gpio gpio 00 01 gpio gpio gpio gpio gpio pld out pld in pld in 00 10 gpio gpio gpio gpio pld out pld in pld in pld in 00 11 gpio gpio gpio pld out pld out pld in pld in pld in 01 00 gpio pld out pld in pld in gpio gpio gpio gpio 01 01 gpio pld out pld in pld in gpio pld out pld in pld in 01 10 gpio pld out pld in pld in pld out pld in pld in pld in 01 11 gpio gpio gpio pld out pld out pld in pld in pld in 10 00 pld out pld in pld in pld in gpio gpio gpio gpio 10 01 pld out pld in pld in pld in gpio pld out pld in pld in 10 10 pld out pld in pld in pld in pld out pld in pld in pld in 10 11 gpio gpio gpio pld out pld out pld in pld in pld in table 9 C SX1502 pld modes settings 4.7.3 sx1503 each of the two i/o banks of the sx1503 i/os can be configured as per the SX1502. regpldmodeb sx1503 i/os 5:4 1:0 15 14 13 12 11 10 9 8 00 00 gpio gpio gpio gpio gpio gpio gpio gpio 00 01 gpio gpio gpio gpio gpio pld out pld in pld in 00 10 gpio gpio gpio gpio pld out pld in pld in pld in 00 11 gpio gpio gpio pld out pld out pld in pld in pld in 01 00 gpio pld out pld in pld in gpio gpio gpio gpio 01 01 gpio pld out pld in pld in gpio pld out pld in pld in 01 10 gpio pld out pld in pld in pld out pld in pld in pld in 01 11 gpio gpio gpio pld out pld out pld in pld in pld in 10 00 pld out pld in pld in pld in gpio gpio gpio gpio 10 01 pld out pld in pld in pld in gpio pld out pld in pld in 10 10 pld out pld in pld in pld in pld out pld in pld in pld in 10 11 gpio gpio gpio pld out pld out pld in pld in pld in table 10 C sx1503 pld modes settings (bank b) regpldmodea sx1503 i/os 5:4 1:0 7 6 5 4 3 2 1 0 00 00 gpio gpio gpio gpio gpio gpio gpio gpio 00 01 gpio gpio gpio gpio gpio pld out pld in pld in 00 10 gpio gpio gpio gpio pld out pld in pld in pld in 00 11 gpio gpio gpio pld out pld out pld in pld in pld in 01 00 gpio pld out pld in pld in gpio gpio gpio gpio 01 01 gpio pld out pld in pld in gpio pld out pld in pld in 01 10 gpio pld out pld in pld in pld out pld in pld in pld in 01 11 gpio gpio gpio pld out pld out pld in pld in pld in 10 00 pld out pld in pld in pld in gpio gpio gpio gpio 10 01 pld out pld in pld in pld in gpio pld out pld in pld in 10 10 pld out pld in pld in pld in pld out pld in pld in pld in 10 11 gpio gpio gpio pld out pld out pld in pld in pld in table 11 C sx1503 pld modes settings (bank b) 4.7.4 tutorial the generic method described in this paragraph can be applied to any of the sx1501, SX1502 or sx1503.
advanced communications & sensing rev 8 C 18 th feb. 2009 www.semtech.com 19 sx1501/SX1502/sx1503 4/8/16 channel low voltage gpio example: we want to implement an and gate between i /o[0] and io[1] on SX1502 1. identify in the tables above the regpldmode sett ing to be programmed. what we need corresponds to the second line of the SX1502 pld table => regpldmode = xx00xx 01 2. fill corresponding regpldtablex with the wanted truth table. as mentioned in regpldmode description, using pld 2 -to-1 mode on i/0[0-2] implies to fill the truth table located in regpldtable0(3:0) i/o[1] i/o[0] i/o[2] 0 0 0 0 1 0 1 0 0 1 1 1 => regpldtable0 = xxxx 1000
advanced communications & sensing rev 8 C 18 th feb. 2009 www.semtech.com 20 sx1501/SX1502/sx1503 4/8/16 channel low voltage gpio 5 c onfiguration r egisters 5.1 sx1501 4-channel gpio address name description default 0x00 regdata data register 1111 1111 * 0x01 regdir direction register 1111 1111 0x02 regpullup pull-up register 0000 0000 0x03 regpulldown pull-down register 0000 0000 0x04 reserved unused xxxx xxxx 0x05 reginterruptmask interrupt mask register 1111 1111 0x06 regsensehigh unused xxxx xxxx 0x07 regsenselow sense register 0000 0000 0x08 reginterruptsource interrupt source register 0000 0000 0x09 regeventstatus event status register 0000 0000 0x10 regpldmode pld mode register 0000 0000 0x11 regpldtable0 pld truth table 0 0000 0000 0x12 regpldtable1 unused xxxx xxxx 0x13 regpldtable2 pld truth table 2 0000 0000 0x14 regpldtable3 unused xxxx xxxx 0x15 regpldtable4 unused xxxx xxxx 0xab regadvanced advanced settings register 0000 0000 *bits set as output take 1 as default value. table 12 C sx1501 configuration registers overview addr name default bits description 7:4 reserved. must be set to 1 (default value) 0x00 regdata 0xff 3:0 write: data to be output to the output-configured i os read: data seen at the ios, independent of the dire ction configured. 7:4 reserved. must be set to 1 (default value) 0x01 regdir 0xff 3:0 configures direction for each io. 0 : io is configured as an output 1 : io is configured as an input 7:4 reserved. must be set to 0 (default value) 0x02 regpullup 0x00 3:0 enables the pull-up for each io 0 : pull-up is disabled 1 : pull-up is enabled 7:4 reserved. must be set to 0 (default value) 0x03 regpulldown 0x00 3:0 enables the pull-down for each io 0 : pull-down is disabled 1 : pull-down is enabled 0x04 reserved 0xxx 7:0 unused 7:4 reserved. must be set to 1 (default value) 0x05 reginterruptmask 0xff 3:0 configures which [input-configured] io will trigger an interrupt on nint pin 0 : an event on this io will trigger an interrupt 1 : an event on this io will not trigger an interru pt 0x06 regsensehigh 0xxx 7:0 unused 7:6 edge sensitivity of i/o[3] 5:4 edge sensitivity of i/o[2] 3:2 edge sensitivity of i/o[1] 0x07 regsenselow 0x00 1:0 edge sensitivity of i/o[0] 00 : none 01 : rising 10 : falling 11 : both 7:4 reserved. must be set to 0 (default value) 0x08 reginterruptsource 0x00 3:0 interrupt source (from ios set in reginterruptmask) 0 : no interrupt has been triggered by this io 1 : an interrupt has been triggered by this io (an event as configured in relevant regsense register occured). writing '1' clears the bit in reginterruptsource an d in regeventstatus. when all bits are cleared, nint signal goes back hi gh. 0x09 0x00 7:4 reserved. must be set to 0 (default value)
advanced communications & sensing rev 8 C 18 th feb. 2009 www.semtech.com 21 sx1501/SX1502/sx1503 4/8/16 channel low voltage gpio addr name default bits description regeventstatus 3:0 event status of all ios. 0 : no event has occured on this io 1 : an event has occured on this io (an edge as con figured in relevant regsense register occured). writing '1' clears the bit in regeventstatus and in reginterruptsource if relevant. if the edge sensitivity of the io is changed, the b it(s) will be cleared automatically 7:2 reserved. must be set to 0 (default value) 0x10 regpldmode 0x00 1:0 pldmode 00 : pld disabled C normal gpio mode for i/o[3:0] 01 : pld 2-to-1 mode C i/o[2] is a decode of i/o[1: 0] as defined in regpldtable0 10 : pld 3-to-1 mode C i/o[3] is a decode of i/o[2: 0] as defined in regpldtable2 11 : not used 7:4 reserved. must be set to 0 (default value) 3 value to be output on i/o[2] when i/o[1:0] = 11 2 value to be output on i/o[2] when i/o[1:0] = 10 1 value to be output on i/o[2] when i/o[1:0] = 01 0x11 regpldtable0 0x00 0 value to be output on i/o[2] when i/o[1:0] = 00 applies only when pldmode is set to pld 2-to-1 mode 0x12 regpldtable1 0xxx 7:0 unused 7 value to be output on i/o[3] when i/o[2:0] = 111 6 value to be output on i/o[3] when i/o[2:0] = 110 5 value to be output on i/o[3] when i/o[2:0] = 101 4 value to be output on i/o[3] when i/o[2:0] = 100 3 value to be output on i/o[3] when i/o[2:0] = 011 2 value to be output on i/o[3] when i/o[2:0] = 010 1 value to be output on i/o[3] when i/o[2:0] = 001 0x13 regpldtable2 0x00 0 value to be output on i/o[3] when i/o[2:0] = 000 applies only when pldmode is set to pld 3-to-1 mode 0x14 regpldtable3 0xxx 7:0 unused 0x15 regpldtable4 0xxx 7:0 unused 7.2 reserved. must be set to 0 (default value) 1 boost mode (cf. 2.2.1) 0: off 1: on 0xab regadvanced 0x00 0 reserved. must be set to 0 (default value) table 13 C sx1501 configuration register s description 5.2 SX1502 8-channel gpio address name description default 0x00 regdata data register 1111 1111 * 0x01 regdir direction register 1111 1111 0x02 regpullup pull-up register 0000 0000 0x03 regpulldown pull-down register 0000 0000 0x04 reserved unused xxxx xxxx 0x05 reginterruptmask interrupt mask register 1111 1111 0x06 regsensehigh sense register for i/o[7:4] 0000 0000 0x07 regsenselow sense register for i/o[3:0] 0000 0000 0x08 reginterruptsource interrupt source register 0000 0000 0x09 regeventstatus event status register 0000 0000 0x10 regpldmode pld mode register 0000 0000 0x11 regpldtable0 pld truth table 0 0000 0000 0x12 regpldtable1 pld truth table 1 0000 0000 0x13 regpldtable2 pld truth table 2 0000 0000 0x14 regpldtable3 pld truth table 3 0000 0000 0x15 regpldtable4 pld truth table 4 0000 0000 0xab regadvanced advanced settings register 0000 0000 *bits set as output take 1 as defau lt value. table 14 C SX1502 configuration registers overview addr name default bits description 0x00 regdata 0xff 7:0 write: data to be output to the output-configured i os read: data seen at the ios, independent of the dire ction configured. 0x01 regdir 0xff 7:0 configures direction for each io. 0 : io is configured as an output 1 : io is configured as an input
advanced communications & sensing rev 8 C 18 th feb. 2009 www.semtech.com 22 sx1501/SX1502/sx1503 4/8/16 channel low voltage gpio addr name default bits description 0x02 regpullup 0x00 7:0 enables the pull-up for each io 0 : pull-up is disabled 1 : pull-up is enabled 0x03 regpulldown 0x00 7:0 enables the pull-down for each io 0 : pull-down is disabled 1 : pull-down is enabled 0x04 reserved 0xxx 7:0 unused 0x05 reginterruptmask 0xff 7:0 configures which [input-configured] io will trigger an interrupt on nint pin 0 : an event on this io will trigger an interrupt 1 : an event on this io will not trigger an interru pt 7:6 edge sensitivity of i/o[7] 5:4 edge sensitivity of i/o[6] 3:2 edge sensitivity of i/o[5] 0x06 regsensehigh 0x00 1:0 edge sensitivity of i/o[4] 00 : none 01 : rising 10 : falling 11 : both 7:6 edge sensitivity of i/o[3] 5:4 edge sensitivity of i/o[2] 3:2 edge sensitivity of i/o[1] 0x07 regsenselow 0x00 1:0 edge sensitivity of i/o[0] 00 : none 01 : rising 10 : falling 11 : both 0x08 reginterruptsource 0x00 7:0 interrupt source (from ios set in reginterruptmask) 0 : no interrupt has been triggered by this io 1 : an interrupt has been triggered by this io (an event as configured in relevant regsense register occured). writing '1' clears the bit in reginterruptsource an d in regeventstatus when all bits are cleared, nint signal goes back hi gh. 0x09 regeventstatus 0x00 7:0 event status of all ios. 0 : no event has occured on this io 1 : an event has occured on this io (an edge as con figured in relevant regsense register occured). writing '1' clears the bit in regeventstatus and in reginterruptsource if relevant. if the edge sensitivity of the io is changed, the b it(s) will be cleared automatically 7:6 reserved. must be set to 0 (default value) 5:4 pldmodehigh (applies to i/o[7:4]) 00 : pld disabled C normal gpio mode for i/o[7:4] 01 : pld 2-to-1 mode C i/o[6] is a decode of i/o[5: 4] as defined in regpldtable0 10 : pld 3-to-1 mode C i/o[7] is a decode of i/o[6: 4] as defined in regpldtable1 11 : reserved 3:2 reserved. must be set to 0 (default value) 0x10 regpldmode 0x00 1:0 pldmodelow (applies to i/o[3:0]) 00 : pld disabled C normal gpio mode for i/o[3:0] 01 : pld 2-to-1 mode C i/o[2] is a decode of i/o[1: 0] as defined in regpldtable0 10 : pld 3-to-1 mode C i/o[3] is a decode of i/o[2: 0] as defined in regpldtable2 11 : pld 3-to-2 mode C i/o[4:3] are decodes of i/o[ 2:0] as defined in regpldtable3 and regpldtable4 7 value to be output on i/o[6] when i/o[5:4] = 11 6 value to be output on i/o[6] when i/o[5:4] = 10 5 value to be output on i/o[6] when i/o[5:4] = 01 4 value to be output on i/o[6] when i/o[5:4] = 00 applies only when pldmodehigh is set to pld 2- to-1 mode 3 value to be output on i/o[2] when i/o[1:0] = 11 2 value to be output on i/o[2] when i/o[1:0] = 10 1 value to be output on i/o[2] when i/o[1:0] = 01 0x11 regpldtable0 0x00 0 value to be output on i/o[2] when i/o[1:0] = 00 applies only when pldmodelow is set to pld 2- to-1 mode 7 value to be output on i/o[7] when i/o[6:4] = 111 6 value to be output on i/o[7] when i/o[6:4] = 110 5 value to be output on i/o[7] when i/o[6:4] = 101 4 value to be output on i/o[7] when i/o[6:4] = 100 3 value to be output on i/o[7] when i/o[6:4] = 011 2 value to be output on i/o[7] when i/o[6:4] = 010 1 value to be output on i/o[7] when i/o[6:4] = 001 0x12 regpldtable1 0x00 0 value to be output on i/o[7] when i/o[6:4] = 000 applies only when pldmodehigh is set to pld 3- to-1 mode 7 value to be output on i/o[3] when i/o[2:0] = 111 6 value to be output on i/o[3] when i/o[2:0] = 110 5 value to be output on i/o[3] when i/o[2:0] = 101 4 value to be output on i/o[3] when i/o[2:0] = 100 3 value to be output on i/o[3] when i/o[2:0] = 011 2 value to be output on i/o[3] when i/o[2:0] = 010 0x13 regpldtable2 0x00 1 value to be output on i/o[3] when i/o[2:0] = 001 applies only when pldmodelow is set to pld 3- to-1 mode
advanced communications & sensing rev 8 C 18 th feb. 2009 www.semtech.com 23 sx1501/SX1502/sx1503 4/8/16 channel low voltage gpio addr name default bits description 0 value to be output on i/o[3] when i/o[2:0] = 000 7 value to be output on i/o[4] when i/o[2:0] = 111 6 value to be output on i/o[4] when i/o[2:0] = 110 5 value to be output on i/o[4] when i/o[2:0] = 101 4 value to be output on i/o[4] when i/o[2:0] = 100 3 value to be output on i/o[4] when i/o[2:0] = 011 2 value to be output on i/o[4] when i/o[2:0] = 010 1 value to be output on i/o[4] when i/o[2:0] = 001 0x14 regpldtable3 0x00 0 value to be output on i/o[4] when i/o[2:0] = 000 applies only when pldmodelow is set to pld 3- to-2 mode 7 value to be output on i/o[3] when i/o[2:0] = 111 6 value to be output on i/o[3] when i/o[2:0] = 110 5 value to be output on i/o[3] when i/o[2:0] = 101 4 value to be output on i/o[3] when i/o[2:0] = 100 3 value to be output on i/o[3] when i/o[2:0] = 011 2 value to be output on i/o[3] when i/o[2:0] = 010 1 value to be output on i/o[3] when i/o[2:0] = 001 0x15 regpldtable4 0x00 0 value to be output on i/o[3] when i/o[2:0] = 000 applies only when pldmodelow is set to pld 3- to-2 mode 7:2 reserved. must be set to 0 (default value) 1 boost mode (cf. 2.2.1) 0: off 1: on 0xab regadvanced 0x00 0 reserved. must be set to 0 (default value) table 15 C SX1502 configuration registers descripti on 5.3 sx1503 16-channel gpio address name description default 0x00 regdatab data register for bank b i/o[15:8] 1111 1111 * 0x01 regdataa data register for bank a i/o[7:0] 1111 1111 * 0x02 regdirb direction register for bank b i/o[15:8] 1111 1111 0x03 regdira direction register for bank a i/o[7:0] 1111 1111 0x04 regpullupb pull-up register for bank b i/o[15:8] 0000 0000 0x05 regpullupa pull-up register for bank a i/o[7:0] 0000 0000 0x06 regpulldownb pull-down register for bank b i/o[15:8] 0000 0000 0x07 regpulldowna pull-down register for bank a i/o[7:0] 0000 0000 0x08 reginterruptmaskb interrupt mask register for bank b i/o[15:8] 1111 1 111 0x09 reginterruptmaska interrupt mask register for bank a i/o[7:0] 1111 11 11 0x0a regsensehighb sense register for i/o[15:12] 0000 0000 0x0b regsensehigha sense register for i/o[7:4] 0000 0000 0x0c regsenselowb sense register for i/o[11:8] 0000 0000 0x0d regsenselowa sense register for i/o[3:0] 0000 0000 0x0e reginterruptsourceb interrupt source register for bank b i/o[15:8] 0000 0000 0x0f reginterruptsourcea interrupt source register for bank a i/o[7:0] 0000 0000 0x10 regeventstatusb event status register for bank b i/o[15:8] 0000 000 0 0x11 regeventstatusa event status register for bank a i/o[7:0] 0000 0000 0x20 regpldmodeb pld mode register for bank b i/o[15:8] 0000 0000 0x21 regpldmodea pld mode register for bank a i/o[7:0] 0000 0000 0x22 regpldtable0b pld truth table 0 for bank b i/o[15:8] 0000 0000 0x23 regpldtable0a pld truth table 0 for bank a i/o[7:0] 0000 0000 0x24 regpldtable1b pld truth table 1 for bank b i/o[15:8] 0000 0000 0x25 regpldtable1a pld truth table 1 for bank a i/o[7:0] 0000 0000 0x26 regpldtable2b pld truth table 2 for bank b i/o[15:8] 0000 0000 0x27 regpldtable2a pld truth table 2 for bank a i/o[7:0] 0000 0000 0x28 regpldtable3b pld truth table 3 for bank b i/o[15:8] 0000 0000 0x29 regpldtable3a pld truth table 3 for bank a i/o[7:0] 0000 0000 0x2a regpldtable4b pld truth table 4 for bank b i/o[15:8] 0000 0000 0x2b regpldtable4a pld truth table 4 for bank a i/o[7:0] 0000 0000 0xad regadvanced advanced settings register 0000 0000 *bits set as output take 1 as default value. table 16 C sx1503 configuration registers overview addr name default bits description
advanced communications & sensing rev 8 C 18 th feb. 2009 www.semtech.com 24 sx1501/SX1502/sx1503 4/8/16 channel low voltage gpio addr name default bits description 0x00 regdatab 0xff 7:0 write: data to be output to the output-configured i os read: data seen at the ios, independent of the dire ction configured. 0x01 regdataa 0xff 7:0 write: data to be output to the output-configured i os read: data seen at the ios, independent of the dire ction configured. 0x02 regdirb 0xff 7:0 configures direction for each io. 0 : io is configured as an output 1 : io is configured as an input 0x03 regdira 0xff 7:0 configures direction for each io. 0 : io is configured as an output 1 : io is configured as an input 0x04 regpullupb 0x00 7:0 enables the pull-up for each io 0 : pull-up is disabled 1 : pull-up is enabled 0x05 regpullupa 0x00 7:0 enables the pull-up for each io 0 : pull-up is disabled 1 : pull-up is enabled 0x06 regpulldownb 0x00 7:0 enables the pull-down for each io 0 : pull-down is disabled 1 : pull-down is enabled 0x07 regpulldowna 0x00 7:0 enables the pull-down for each io 0 : pull-down is disabled 1 : pull-down is enabled 0x08 reginterruptmaskb 0xff 7:0 configures which [input-configured] io will trigger an interrupt on nint pin 0 : an event on this io will trigger an interrupt 1 : an event on this io will not trigger an interru pt 0x09 reginterruptmaska 0xff 7:0 configures which [input-configured] io will trigger an interrupt on nint pin 0 : an event on this io will trigger an interrupt 1 : an event on this io will not trigger an interru pt 7:6 edge sensitivity of i/o[15] 5:4 edge sensitivity of i/o[14] 3:2 edge sensitivity of i/o[13] 0x0a regsensehighb 0x00 1:0 edge sensitivity of i/o[12] 00 : none 01 : rising 10 : falling 11 : both 7:6 edge sensitivity of i/o[7] 5:4 edge sensitivity of i/o[6] 3:2 edge sensitivity of i/o[5] 0x0b regsensehigha 0x00 1:0 edge sensitivity of i/o[4] 00 : none 01 : rising 10 : falling 11 : both 7:6 edge sensitivity of i/o[11] 5:4 edge sensitivity of i/o[10] 3:2 edge sensitivity of i/o[9] 0x0c regsenselowb 0x00 1:0 edge sensitivity of i/o[8] 00 : none 01 : rising 10 : falling 11 : both 7:6 edge sensitivity of i/o[3] 5:4 edge sensitivity of i/o[2] 3:2 edge sensitivity of i/o[1] 0x0d regsenselowa 0x00 1:0 edge sensitivity of i/o[0] 00 : none 01 : rising 10 : falling 11 : both 0x0e reginterruptsourceb 0x00 7:0 interrupt source (from ios set in reginterruptmaskb ) 0 : no interrupt has been triggered by this io 1 : an interrupt has been triggered by this io (an event as configured in relevant regsense register occured). writing '1' clears the bit in reginterruptsourceb a nd in regeventstatusb when all bits of both reginterruptsourcea/b are cle ared, nint signal goes back high. 0x0f reginterruptsourcea 0x00 7:0 interrupt source (from ios set in reginterruptmaska ) 0 : no interrupt has been triggered by this io 1 : an interrupt has been triggered by this io (an event as configured in relevant regsense register occured). writing '1' clears the bit in reginterruptsourcea a nd in regeventstatusa when all bits of both reginterruptsourcea/b are cle ared, nint signal goes back high. 0x10 regeventstatusb 0x00 7:0 event status of all ios. 0 : no event has occured on this io 1 : an event has occured on this io (an edge as con figured in relevant regsense register occured). writing '1' clears the bit in regeventstatusb and i n reginterruptsourceb if relevant. if the edge sensitivity of the io is changed, the b it(s) will be cleared automatically
advanced communications & sensing rev 8 C 18 th feb. 2009 www.semtech.com 25 sx1501/SX1502/sx1503 4/8/16 channel low voltage gpio addr name default bits description 0x11 regeventstatusa 0x00 7:0 event status of all ios. 0 : no event has occured on this io 1 : an event has occured on this io (an edge as con figured in relevant regsense register occured). writing '1' clears the bit in regeventstatusa and i n reginterruptsourcea if relevant. if the edge sensitivity of the io is changed, the b it(s) will be cleared automatically 7:6 reserved. must be set to 0 (default value) 5:4 pldmodehighb (applies to i/o[15:12]) 00 : pld disabled C normal gpio mode for i/o[15:12] 01 : pld 2-to-1 mode C i/o[14] is a decode of i/o[1 3:12] as defined in regpldtable0b 10 : pld 3-to-1 mode C i/o[15] is a decode of i/o[1 4:12] as defined in regpldtable1b 11 : reserved 3:2 reserved. must be set to 0 (default value) 0x20 regpldmodeb 0x00 1:0 pldmodelowb (applies to i/o[11:8]) 00 : pld disabled C normal gpio mode for i/o[11:8] 01 : pld 2-to-1 mode C i/o[10] is a decode of i/o[9 :8] as defined in regpldtable0b 10 : pld 3-to-1 mode C i/o[11] is a decode of i/o[1 0:8] as defined in regpldtable2b 11 : pld 3-to-2 mode C i/o[12:11] are decodes of i/ o[10:8] as defined in regpldtable3b and regpldtable4b 7:6 reserved. must be set to 0 (default value) 5:4 pldmodehigha (applies to i/o[7:4]) 00 : pld disabled C normal gpio mode for i/o[7:4] 01 : pld 2-to-1 mode C i/o[6] is a decode of i/o[5: 4] as defined in regpldtable0a 10 : pld 3-to-1 mode C i/o[7] is a decode of i/o[6: 4] as defined in regpldtable1a 11 : reserved 3:2 reserved. must be set to 0 (default value) 0x21 regpldmodea 0x00 1:0 pldmodelowa (applies to i/o[3:0]) 00 : pld disabled C normal gpio mode for i/o[3:0] 01 : pld 2-to-1 mode C i/o[2] is a decode of i/o[1: 0] as defined in regpldtable0a 10 : pld 3-to-1 mode C i/o[3] is a decode of i/o[2: 0] as defined in regpldtable2a 11 : pld 3-to-2 mode C i/o[4:3] are decodes of i/o[ 2:0] as defined in regpldtable3a and regpldtable4a 7 value to be output on i/o[14] when i/o[13:12] = 1 1 6 value to be output on i/o[14] when i/o[13:12] = 1 0 5 value to be output on i/o[14] when i/o[13:12] = 0 1 4 value to be output on i/o[14] when i/o[13:12] = 0 0 applies only when pldmodehighb is set to pld 2-to-1 mode 3 value to be output on i/o[10] when i/o[9:8] = 11 2 value to be output on i/o[10] when i/o[9:8] = 10 1 value to be output on i/o[10] when i/o[9:8] = 01 0x22 regpldtable0b 0x00 0 value to be output on i/o[10] when i/o[9:8] = 00 applies only when pldmodelowb is set to pld 2-to-1 mode 7 value to be output on i/o[6] when i/o[5:4] = 11 6 value to be output on i/o[6] when i/o[5:4] = 10 5 value to be output on i/o[6] when i/o[5:4] = 01 4 value to be output on i/o[6] when i/o[5:4] = 00 applies only when pldmodehigha is set to pld 2-to-1 mode 3 value to be output on i/o[2] when i/o[1:0] = 11 2 value to be output on i/o[2] when i/o[1:0] = 10 1 value to be output on i/o[2] when i/o[1:0] = 01 0x23 regpldtable0a 0x00 0 value to be output on i/o[2] when i/o[1:0] = 00 applies only when pldmodelowa is set to pld 2-to-1 mode 7 value to be output on i/o[15] when i/o[14:12] = 1 11 6 value to be output on i/o[15] when i/o[14:12] = 1 10 5 value to be output on i/o[15] when i/o[14:12] = 1 01 4 value to be output on i/o[15] when i/o[14:12] = 1 00 3 value to be output on i/o[15] when i/o[14:12] = 0 11 2 value to be output on i/o[15] when i/o[14:12] = 0 10 1 value to be output on i/o[15] when i/o[14:12] = 0 01 0x24 regpldtable1b 0x00 0 value to be output on i/o[15] when i/o[14:12] = 0 00 applies only when pldmodehighb is set to pld 3-to-1 mode 7 value to be output on i/o[7] when i/o[6:4] = 111 6 value to be output on i/o[7] when i/o[6:4] = 110 5 value to be output on i/o[7] when i/o[6:4] = 101 4 value to be output on i/o[7] when i/o[6:4] = 100 3 value to be output on i/o[7] when i/o[6:4] = 011 2 value to be output on i/o[7] when i/o[6:4] = 010 1 value to be output on i/o[7] when i/o[6:4] = 001 0x25 regpldtable1a 0x00 0 value to be output on i/o[7] when i/o[6:4] = 000 applies only when pldmodehigha is set to pld 3-to-1 mode 7 value to be output on i/o[11] when i/o[10:8] = 11 1 0x26 regpldtable2b 0x00 6 value to be output on i/o[11] when i/o[10:8] = 11 0 applies only when pldmodelowb is set to pld
advanced communications & sensing rev 8 C 18 th feb. 2009 www.semtech.com 26 sx1501/SX1502/sx1503 4/8/16 channel low voltage gpio addr name default bits description 5 value to be output on i/o[11] when i/o[10:8] = 10 1 4 value to be output on i/o[11] when i/o[10:8] = 10 0 3 value to be output on i/o[11] when i/o[10:8] = 01 1 2 value to be output on i/o[11] when i/o[10:8] = 01 0 1 value to be output on i/o[11] when i/o[10:8] = 00 1 0 value to be output on i/o[11] when i/o[10:8] = 00 0 3-to-1 mode 7 value to be output on i/o[3] when i/o[2:0] = 111 6 value to be output on i/o[3] when i/o[2:0] = 110 5 value to be output on i/o[3] when i/o[2:0] = 101 4 value to be output on i/o[3] when i/o[2:0] = 100 3 value to be output on i/o[3] when i/o[2:0] = 011 2 value to be output on i/o[3] when i/o[2:0] = 010 1 value to be output on i/o[3] when i/o[2:0] = 001 0x27 regpldtable2a 0x00 0 value to be output on i/o[3] when i/o[2:0] = 000 applies only when pldmodelowa is set to pld 3-to-1 mode 7 value to be output on i/o[11] when i/o[10:8] = 11 1 6 value to be output on i/o[11] when i/o[10:8] = 11 0 5 value to be output on i/o[11] when i/o[10:8] = 10 1 4 value to be output on i/o[11] when i/o[10:8] = 10 0 3 value to be output on i/o[11] when i/o[10:8] = 01 1 2 value to be output on i/o[11] when i/o[10:8] = 01 0 1 value to be output on i/o[11] when i/o[10:8] = 00 1 0x28 regpldtable3b 0x00 0 value to be output on i/o[11] when i/o[10:8] = 00 0 applies only when pldmodelowb is set to pld 3-to-2 mode 7 value to be output on i/o[3] when i/o[2:0] = 111 6 value to be output on i/o[3] when i/o[2:0] = 110 5 value to be output on i/o[3] when i/o[2:0] = 101 4 value to be output on i/o[3] when i/o[2:0] = 100 3 value to be output on i/o[3] when i/o[2:0] = 011 2 value to be output on i/o[3] when i/o[2:0] = 010 1 value to be output on i/o[3] when i/o[2:0] = 001 0x29 regpldtable3a 0x00 0 value to be output on i/o[3] when i/o[2:0] = 000 applies only when pldmodelowa is set to pld 3-to-2 mode 7 value to be output on i/o[12] when i/o[10:8] = 11 1 6 value to be output on i/o[12] when i/o[10:8] = 11 0 5 value to be output on i/o[12] when i/o[10:8] = 10 1 4 value to be output on i/o[12] when i/o[10:8] = 10 0 3 value to be output on i/o[12] when i/o[10:8] = 01 1 2 value to be output on i/o[12] when i/o[10:8] = 01 0 1 value to be output on i/o[12] when i/o[10:8] = 00 1 0x2a regpldtable4b 0x00 0 value to be output on i/o[12] when i/o[10:8] = 00 0 applies only when pldmodelowb is set to pld 3-to-2 mode 7 value to be output on i/o[4] when i/o[2:0] = 111 6 value to be output on i/o[4] when i/o[2:0] = 110 5 value to be output on i/o[4] when i/o[2:0] = 101 4 value to be output on i/o[4] when i/o[2:0] = 100 3 value to be output on i/o[4] when i/o[2:0] = 011 2 value to be output on i/o[4] when i/o[2:0] = 010 1 value to be output on i/o[4] when i/o[2:0] = 001 0x2b regpldtable4a 0x00 0 value to be output on i/o[4] when i/o[2:0] = 000 applies only when pldmodelowa is set to pld 3-to-2 mode 7:3 reserved. must be set to 0 (default value) 2 autoclear nint on regdata read (cf. 4.6) 0: off.reginterruptsource must be manually cleared directly or via regeventstatus 1: on.reginterruptsource is automatically cleared w hen regdatab or regdataa is read 1 boost mode (cf. 2.2.1) 0: off 1: on 0xad regadvanced 0x00 0 reserved. must be set to 0 (default value) table 17 C sx1503 configuration registers descripti on
advanced communications & sensing rev 8 C 18 th feb. 2009 www.semtech.com 27 sx1501/SX1502/sx1503 4/8/16 channel low voltage gpio 6 a pplication i nformation 6.1 typical application circuit figure 12 - typical application schematic 6.2 typical led operation typical led operation is described below. the led i s usually connected to a high voltage (vbat) to tak e advantage of the high sink current of the i/o and t o accommodate high led threshold voltages (vled). vccx iox vbat vccx vled * * led colour/technology dependent sx1501/2/3 iol r figure 13 C typical led operation important: vccx must exceed vbat-vled (vccx = vbat is recomme nded) else the led will never be completely off r must be calculated for iol not to exceed its max spec (cf. table 5) 6.2.1 led on/off control regdir[x] regdata[x] led on 0 led off 0 (output) 1 table 18 C led on/off control vddm nreset scl sda addr gnd vcc1 i/o[0] i/o[1] i/o[2] i/o[3] nint i/o[4] i/o[5] i/o[6] i/o[7] vcc2 SX1502 scl sda i/o i/o 3.3v 2.5v 1.2v 5v optional (depends on the application) 5v host controlle r
advanced communications & sensing rev 8 C 18 th feb. 2009 www.semtech.com 28 sx1501/SX1502/sx1503 4/8/16 channel low voltage gpio 6.2.2 led intensity control when the max iol spec is not enough it is possible to drive simultaneously multiple i/os connected tog ether hence increasing the total sink capability. example: on an SX1502, by driving an led with both io[2] and io[3] one can sink up to 24+24 =48ma. driving an led with multiple i/os can also be used to implement more intensity steps for the led. example: with two i/os capable of sinking each 24ma the led can sink a total of 0ma (no i/o set to 0 ), 24ma (one i/o set to 0) or 48ma (both i/os set to 0) => 3 led intensity steps ( 4 steps with 3 i/os, 5 steps with 4 i/os, etc) 6.3 keypad implementation sx1501, SX1502, and sx1503 can be used to implement keypad applications up to 8x8 matrix (i.e. 64 keys ) example: we want to implement a 4x4matrix keypad on SX1502 io7 io6 io5 io4 io3 io2 io1 io0 SX1502 io[7-0] as inputs with internal pull-ups enabled figure 14 C 4x4 keypad connection to SX1502 1. set all i/os as inputs with internal pull-up (re gdir = 0xff, regpullup = 0xff) 2. set nint to be triggered on any ios falling edg e (reginterruptmask = 0x00, regsensehigh = 0xaa, regsenselow = 0xaa) 3. when nint goes low read regdata (or reginterrupt source) to know the x:y coordinates of the button which has been pressed. 4. clear nint (reginterruptsource = 0xff, can be do ne automatically on sx1503 depending on regadvanced setting) 5. restart from point 3 6.4 level shifter implementation hints because of their i/o banks with independent supply voltages between 1.2v and 5.5v, the SX1502 and sx15 03 can be easily used to perform level shifting of sig nals from one i/o bank to an other (uc reads i/o fr om one i/o bank and sends it back to the other i/o bank) this can save significant bom cost in a final appli cation where only a few slow signals need to be lev el-shifted.
advanced communications & sensing rev 8 C 18 th feb. 2009 www.semtech.com 29 sx1501/SX1502/sx1503 4/8/16 channel low voltage gpio 7 p ackaging i nformation 7.1 qfn-ut 20-pin outline drawing qfn-ut 20-pin, 3 x 3 mm, 0.4 mm pitch figure 15 - packaging information C qfn-ut 20-pin o utline drawing 7.2 qfn-ut 20-pin land pattern figure 16 - packaging information C qfn-ut 20-pin l and pattern
advanced communications & sensing rev 8 C 18 th feb. 2009 www.semtech.com 30 sx1501/SX1502/sx1503 4/8/16 channel low voltage gpio 7.3 qfn-ut 28-pin outline drawing qfn-ut 28-pin, 4 x 4 mm, 0.4 mm pitch figure 17 - packaging information C qfn-ut 28-pin o utline drawing 7.4 qfn-ut 28-pin land pattern figure 18 - packaging information C qfn-ut 28-pin l and pattern 7.5 tssop 20-pin outline drawing
advanced communications & sensing rev 8 C 18 th feb. 2009 www.semtech.com 31 sx1501/SX1502/sx1503 4/8/16 channel low voltage gpio figure 19 - packaging information C tssop 20-pin ou tline drawing 7.6 tssop 20-pin land pattern figure 20 - packaging information C tssop 20-pin la nd pattern
advanced communications & sensing rev 8 C 18 th feb. 2009 www.semtech.com 32 sx1501/SX1502/sx1503 4/8/16 channel low voltage gpio 7.7 tssop 28-pin outline drawing figure 21 - packaging information C tssop 28-pin ou tline drawing 7.8 tssop 28-pin land pattern figure 22 - packaging information C tssop 28-pin la nd pattern
advanced communications & sensing rev 8 C 18 th feb. 2009 www.semtech.com 33 sx1501/SX1502/sx1503 4/8/16 channel low voltage gpio 8 s oldering p rofile the soldering reflow profile for the sx1501, SX1502 and sx1503 is described in the standard ipc/jedec j- std-020c. for detailed information please go to http://www.jedec.org/download/search/jstd020c.pdf figure 23 - classification reflow profile (ipc/jede c j-std-020c)
advanced communications & sensing rev 8 C 18 th feb. 2009 www.semtech.com 34 sx1501/SX1502/sx1503 4/8/16 channel low voltage gpio contact information ? semtech 2009 all rights reserved. reproduction in whole or in pa rt is prohibited without the prior written consent of the copyright owner. the information presented in this document does not form part of any quotation or con tract, is believed to be accurate and reliable and may be cha nged without notice. no liability will be accepted b y the publisher for any consequence of its use. publicati on thereof does not convey nor imply any license un der patent or other industrial or intellectual property rights . semtech assumes no responsibility or liability wh atsoever for any failure or unexpec ted operation resulting from misuse, neglect improp er installation, repair or improper handling or unusual physical or electrical stress i ncluding, but n ot limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified range. semtech products are not designed, intended, author ized or warranted to be suitable for use in life-support applications, devi ces or syste ms or other critical applications. inclusion of semtech products in such applications is understood to be undertaken solely at the customers own risk. sh ould a customer purchase or use semtech products for any such unauthorized application, the customer s hall indemnify and hold semtech and its officers, employees, subsidiaries, affiliates, and distributo rs harmless against all claims, costs damages and a ttorney fees which could arise. taiwan tel: 886-2-2748-3380 fax: 886-2-2748-3390 korea tel: 82-2-527-4377 fax: 82-2-527-4376 shanghai tel: 86-21-6391-0830 fax: 86-21-6391-0831 japan tel: 81-3-6408-0950 fax: 81-3-6408-0951 switzerland tel: 41-32-729- 4000 fax: 41-32-729- 4001 united kingdom tel: 44-1794-527- 600 fax: 44-1794-527- 601 france tel: 33-(0)169-28-22- 00 fax: 33-(0)169-28-12- 98 germany tel: 49-(0)8161-140- 123 fax: 49-(0)8161-140- 124 semtech international ag is a wholly- owned subsidiary of semtech corporation, which has its headquarters in the u.s.a

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